Image sensor flip chip package

ABSTRACT

Implementations of semiconductor packages may include: a semiconductor device included within a cavity within a glass block. The package may also include a substrate coupled with a first side of the semiconductor device and two or more edges of the glass block. A fill material may be included between the substrate and the second conductor device and an opaque material may be between a side surface of the semiconductor device and an inner surface of the cavity. The opaque material may be configured to block light from contacting the side surface of the semiconductor device.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of the earlier U.S.Utility Patent Application to Weng-Jin Wu entitled “Image Sensor FlipChip Package,” application Ser. No. 16/183,873, filed Nov. 8, 2018, nowpending, the disclosure of which is hereby incorporated entirely hereinby reference.

BACKGROUND 1. Technical Field

Aspects of this document relate generally to semiconductor packages,such as image sensor devices. Particular implementations may be used incameras or medical imaging devices.

2. Background

Semiconductor devices may include image sensor die coupled to asubstrate through wire bonds over which a transparent sheet of materialis used to expose the die to light. Pixels in the die then receive thelight through the transparent material and generate signals that areprocessed to form an image.

SUMMARY

Implementations of semiconductor packages may include: a semiconductordevice included within a cavity within a glass block. The package mayalso include a substrate coupled with a first side of the semiconductordevice and two or more edges of the glass block. A fill material may beincluded between the substrate and the semiconductor device and anopaque material may be between a side surface of the semiconductordevice and an inner surface of the cavity. The opaque material may beconfigured to block light from contacting the side surface of thesemiconductor device.

Implementations of semiconductor packages may include one, all, or anyof the following:

The semiconductor device may be coupled to the substrate through solder.

The package may include vias within the semiconductor device.

The semiconductor device may be an image sensor.

The package may include two or more standoff structures between theinner cavity within the glass block and a second side of thesemiconductor.

The package may include a plurality of metal traces within the innersurface of the cavity.

Solder balls may be between the second side of the semiconductor deviceand the metal traces.

The cavity may have a shape that is cuboidal.

Implementations of methods of forming semiconductor packages mayinclude: forming a cavity within a glass block and coupling two or morestandoff units to an inner surface of the cavity. The method may alsoinclude bonding a semiconductor device to the two or more standoffs andsealing the semiconductor device within the cavity using an opaquefilling material. The opaque filling material may be configured to blocklight from contacting an edge of the semiconductor device. The methodmay also include mechanically and electrically coupling a substrate tothe semiconductor device and over an opening of the cavity. The methodmay also include underfilling a gap between the substrate, thesemiconductor device, and a side of the glass block surrounding thecavity with an underfill material.

Implementations of method of forming semiconductor packages may includeone, all, or any of the following:

The method may include coupling a ball grid array to a second side ofthe substrate.

The substrate may be coupled to the semiconductor device through solder.

The semiconductor device may be an image sensor.

Vias may be included within the semiconductor device.

The method may include mechanically and electrically coupling asubstrate to the semiconductor device may further include solder balls.

Implementations of methods of forming semiconductor packages mayinclude: forming a cavity within a glass block and coupling a pluralityof metal traces to an inner surface of the cavity. The method mayinclude bonding a semiconductor device into the cavity and sealing thesemiconductor device within the cavity using an opaque filling material.The method may include mechanically and electrically coupling asubstrate to the semiconductor device and over an opening of the cavity.The method may also include underfilling a gap between the substrate,the semiconductor device, and a side of the glass block surrounding thecavity using an underfill material. The opaque filling material may beconfigured to block light from contacting an edge of the semiconductordevice.

Implementations of a method of forming semiconductor packages mayinclude one, all, or any of the following:

The method may include coupling a ball grid array to a second side ofthe substrate.

The substrate may be coupled to the semiconductor device through solder.

The semiconductor device may be an image sensor.

Vias may be included within the semiconductor device.

Bonding may further include bonding solder balls between the second sideof the semiconductor device and the metal traces.

The foregoing and other aspects, features, and advantages will beapparent to those artisans of ordinary skill in the art from theDESCRIPTION and DRAWINGS, and from the CLAIMS.

BRIEF DESCRIPTION OF THE DRAWINGS

Implementations will hereinafter be described in conjunction with theappended drawings, where like designations denote like elements, and:

FIG. 1 is a cross sectional view of an implementation of a semiconductorpackage;

FIG. 2 is a cross sectional view of an another implementation of asemiconductor package;

FIG. 3 is a cross sectional view of an another implementation of asemiconductor package;

FIG. 4 is a cross sectional view of an implementation of an image sensorwafer;

FIG. 5 is a cross section view of an implementation of an image sensorwafer after thinning;

FIG. 6 is a cross sectional view of an implementation of an image sensorwafer/die flipped;

FIG. 7 is a cross sectional view of an implementation of an image sensorwafer/die having vias therethrough;

FIG. 8 is a cross sectional view of an implementation of an image sensorwafer/die thinned and having a redistribution layer;

FIG. 9 is a cross sectional view of an implementation of an image sensordie having interconnects coupled to a redistribution layer;

FIG. 10 is a cross sectional view of an implementation of an imagesensor die flipped;

FIG. 11 is a cross sectional view of an implementation of a flippedimage sensor having interconnects coupled to a redistribution layer;

FIG. 12 is a cross sectional view of an implementation of a glass block;

FIG. 13 is a cross sectional view of an implementation of a glass blockhaving a cavity formed therein;

FIG. 14 is a cross sectional view of an implementation of a glass blockhaving two standoff units coupled therein;

FIG. 15 is a top view of an implementation of a glass block having fourstandoff units coupled therein;

FIG. 16 is a cross sectional view of an implementation of a glass blockhaving a plurality of metal traces therein;

FIG. 17 is a top view of an implementation of a glass block having aplurality of metal traces therein;

FIG. 18 is a side view of an implementation of a glass block having acavity formed therein;

FIG. 19 is a cross sectional view of an implementation of a glass blockhaving two standoff units coupled therein;

FIG. 20 is a cross sectional view of an implementation of asemiconductor device bonded into a cavity;

FIG. 21 is a cross sectional view of an implementation of asemiconductor device sealed within a glass block;

FIG. 22 is a cross sectional view of an implementation of asemiconductor device in a glass block along with a substrate;

FIG. 23 is a cross sectional view of an implementation of a substratecoupled to an image sensor and over an opening of the cavity;

FIG. 24 is a cross sectional view of an implementation of asemiconductor package;

FIG. 25 is a cross sectional view of an implementation of asemiconductor device having interconnects coupled thereto;

FIG. 26 is a side view of an implementation of a glass block having acavity formed therein;

FIG. 27 is a cross sectional view of an implementation of a glass blockhaving a plurality of metal traces therein;

FIG. 28 is a cross sectional view of a semiconductor device bonded intoa cavity of a glass block;

FIG. 29 is a cross sectional view of an implementation of asemiconductor device sealed within a glass bock;

FIG. 30 is a cross sectional view of an implementation of asemiconductor device in a glass block and a substrate;

FIG. 31 is a cross sectional view of an implementation of a substratecoupled to a semiconductor device and over an opening of a cavity;

FIG. 32 is a cross sectional view of an implementation of asemiconductor package;

FIG. 33 is a cross sectional view of an implementation of asemiconductor device having interconnects coupled thereto;

FIG. 34 is a side view of an implementation of a glass block having acavity formed therein;

FIG. 35 is a cross sectional view of an implementation of a glass blockhaving a plurality of metal traces therein;

FIG. 36 is a cross sectional view of a semiconductor device bonded intoa cavity;

FIG. 37 is a cross sectional view of an implementation of an imagesensor sealed within a glass block;

FIG. 38 is a cross sectional view of an implementation of semiconductordevice in a glass block along with a substrate;

FIG. 39 is a cross sectional view of an implementation of a substratecoupled to a semiconductor device and over an opening of a cavity;

FIG. 40 is a cross sectional view of an implementation of asemiconductor package; and

FIG. 41 is a cross sectional view of an implementation of asemiconductor device having interconnects coupled thereto.

DESCRIPTION

This disclosure, its aspects and implementations, are not limited to thespecific components, assembly procedures or method elements disclosedherein. Many additional components, assembly procedures and/or methodelements known in the art consistent with the intended semiconductorpackages will become apparent for use with particular implementationsfrom this disclosure. Accordingly, for example, although particularimplementations are disclosed, such implementations and implementingcomponents may comprise any shape, size, style, type, model, version,measurement, concentration, material, quantity, method element, step,and/or the like as is known in the art for such semiconductor packages,and implementing components and methods, consistent with the intendedoperation and methods.

Referring to FIG. 1, an implementation of a semiconductor package 2 isillustrated. As illustrated, the semiconductor package 2 includes asemiconductor device 4 bonded within a cavity 6. The cavity 6 is formedwithin a glass block 8. In various implementations, the cavity may beformed through etching or casting. The use of a single piece glass blockmay provide strong glass cavity protection. The higher level ofprotection may allow the device to pass higher level reliabilitycriteria. In this document, for the exemplary purposes of thisdisclosure, the material of the block 8 is referred to as glass,however, in various implementations, the material of the block may be awide variety of materials, such as, by non-limiting example, plastic,polymers, silicon, ruby, sapphire, and any other optically transmissivematerial. In some implementations, the block may be made of a materialnot transmissive to visible light, but to non-visible light or otherwavelengths of electromagnetic radiation, such as, by non-limitingexample, infrared light, ultraviolet light, radar, microwave, radiowaves, or any other type of electromagnetic radiation. Correspondingly,the semiconductor die included in the various package implementationsdisclosed herein may include any sensor type designed to detect/respondto any of the types of electromagnetic radiation disclosed in thisdocument.

In the implementation illustrated in FIG. 1, the semiconductor device 4is an image sensor having a colorfilter array (CFA) and microlens(μLens) 10 on the active area of the die. In other implementations,other lenses, filters, or image sensing devices may be included. The CFAand μLens 10 are coupled to a sensor site interconnect 12. An air cavity14 is disposed around the CFA and μLens 10 on the die. The device asdescribed herein may provide a better window to the active area of thedie and allow for a smaller air cavity between the glass and the lenses.The semiconductor device also includes vias 11 coupling the lenses 10 toother parts of the die. In various implementations, the vias 11 may bethrough silicon vias (TSV). In other implementations, the die may beformed of material other than silicon such as, by non-limiting example,silicon-on-insulator, ruby, sapphire, germanium, antimony, arsenic,tellurium, gallium arsenide, indium antimonide, the oxides of metals,any combination thereof, or other suitable semiconductor material.

In the particular implementation illustrated in FIG. 1, the image sensoris positioned on standoff units 16 within the cavity 6. In variousimplementations, two or more standoff units may be included in thepackage. It should be understood that a cross sectional view of thepackage is illustrated where only two standoff units are visible. Insome implementations, four standoff units may be included where astandoff unit is positioned in each corner of where the cavity has ashape that is cuboidal. In other implementations, a single standoff unitmay be used that connects the four corners of the cavity. The standoffunits may be used for electrical connection in some implementations. Invarious implementations, standoff units for electrical connection may beformed of metal, solder, or conductive adhesive. Standoff units mayinclude gold studs, copper bumps, lead tin bumps, nickel or other soldermaterial. In implementations where the standoff units do not have anelectrical connection function, the standoff units may be formed ofpolymer material, glass, ceramic, or other non-conductive material. Thestandoff units may control the gap size/distance between the sensorarray and the dimensions of the cavity.

As illustrated, an optically opaque material 18 is included between thesides of the surface of the semiconductor device 4 and the inner surfaceof the cavity 6. The opaque material may form a hermetic seal betweenthe semiconductor device and the glass. In various implementations, theopaque material may include a light block material where the opaquematerial is optically opaque blocking desired wavelengths of light butnot all wavelengths of light. In various implementations, thewavelengths of light that are blocked may be in the visible spectrum oflight. In other implementations, other wavelengths of light may beblocked, include any wavelengths corresponding with any electromagneticradiation type disclosed in this document.

As illustrated in FIG. 1, a substrate 20 is coupled to a first side 22of the semiconductor device 4 and the corresponding edges of the glassblock 8. In various implementations, the substrate may be an embeddedsubstrate. In implementations with an embedded substrate, one or moredevices may be embedded within the substrate. The embedded devices maybe passive devices, active devices, or a combination of both passive andactive devices. The substrate 20 may be coupled to two or more edges ofthe glass block. The use of a glass block may decrease heating inducedstress for the semiconductor package because glass has a coefficient ofthermal expansion (CTE) that is similar to the CTE of silicon. Thesemiconductor device 4 may be coupled to the substrate through solderballs as illustrated. In various implementations, the semiconductordevice may be coupled to the substrate through other materials. In someimplementations, no wire bonds may be between the semiconductor deviceand the substrate. Use of a flip chip style of bonding between thesemiconductor device and substrate may reduce bonding space and allowfor smaller package footprints. A fill material 26 is included betweenthe substrate and the semiconductor device. The fill material mayprovide insulation for the electrical connections of the semiconductordevice. It may also provide stress relief/support/bonding between thesubstrate and the semiconductor device. In other implementations, wirebonds may be used to couple the die to the substrate.

Referring to FIG. 2, another implementation of a semiconductor packageis illustrated. This implementation includes a semiconductor device 30placed within a cavity 34 of a glass block 32. In variousimplementations, the semiconductor device 30 may be an image sensorhaving lenses 36 on a second side of the semiconductor device. Thelenses may be any lens type disclosed herein. As illustrated, the lenses36 are surrounded by an air cavity 38. The glass block includes aplurality of metal traces 42 within the inner surface of the cavity 34.The semiconductor device is electrically coupled to the metal tracesthrough solder balls 44. In various implementations, other interconnectsmay be used such as by non-limiting example, gold studs or any otherinterconnect type described herein. The metal traces 42 extend along theinner surface of the cavity to the outer edges of the glass block. Anoptically opaque material 46 is between a side surface of thesemiconductor device 30 and the inner surface of cavity. The opaquematerial may block desired wavelengths of light and may be any opticallyopaque material type disclosed herein. The opaque material may form ahermetic seal between the semiconductor device and cavity.

As illustrated, a substrate 47 is mechanically and electrically coupledto the image sensor device through solder balls 48 positioned on themetal traces 42. In various implementations, the electrical connectionsbetween the substrate and the semiconductor device may be gold, copper,nickel, lead/tin, or any other solder material. In some implementations,a metal joint ring (not shown) may be included on an outer edge of thepackage to form a hermetic seal. In such implementations, the metaljoint ring may not be used for electrical connection and may be placedso as to be electrically isolated from the sensor device and othercomponents. A fill material 50 is place between the edge of the glassblock 32, the semiconductor device 30, and the substrate 47. The fillmaterial may be a sealant. The fill material may also insulative to theelectrical connections and may provide any of the other functions offill materials disclosed herein.

Referring to FIG. 3, another implementation of a semiconductor package52 is illustrated. The package includes a semiconductor device 54coupled inside a cavity 56 within glass block 58. As illustrated, thesemiconductor device 54 is an image sensor die having a sensor region 60on a second side of the image sensor die. The image sensor also has asensor site interconnection 62 similar to that as illustrated in otherimplementations in this document. The image sensor die 54 also includesvias 64 extending from the sensor site interconnection 62 to theredistribution layer 66 on the first side of the image sensor die.

As illustrated, this implementation also includes metal traces 68 withinthe inner surface of the glass cavity 56. The metal traces extend frominner cavity to the outer edge 70 of the glass block 58. The imagesensor die is mechanically and electrically coupled to the metal tracesthrough two or more solder balls. In various implementations, the solderballs or interconnects may be formed of gold, nickel, copper, lead/tin,or any other suitable electrically conductive material. A substrate 72is coupled with the first side of the image sensor 54 and the edges 70of the glass block 58 through four interconnects 74. In variousimplementations, the interconnects may be solder balls. In someimplementations, the substrate may be coupled through two or moreinterconnects. A fill material is also placed between the substrate 72and the semiconductor device 54. The fill material may provide a seal tothe package. The fill material may also provide insulation for theelectrical connections and may perform any of the other functions offill materials disclosed in this document.

Referring to FIGS. 4-11, implementations of various methods of formingan image sensor die are illustrated. Referring to FIG. 4, an imagesensor wafer 76 is provided. In FIG. 5, the image sensor wafer 78 isillustrated after having been thinned. The wafer may be thinned by anysuitable method such as by non-limiting example, backgrinding, lapping,wet etching, any combination thereof, or any other technique forremoving backside damage and/or the material of the semiconductorsubstrate substantially uniformly across the largest planar surface ofthe substrate. Referring to FIG. 6, the wafer 80 is illustrated afterhaving been flipped. The wafer may be coupled to a backgrinding tape andflipped using the tape. In other implementations, the wafer may besingulated into individual die and then the die may be flipped. Whilesingulated, the individual dies may be coupled to a picking tape therebymaking flipping easier. Though in other implementations, the dies may beindividually flipped through a pick and place process into carrier tape.

Referring to FIG. 7, an image sensor wafer/die 82 having vias 84 isillustrated. In some implementations, the vias 84 are through siliconvias (TSV) when the wafer is made of silicon. They may be through oxidevias where the wafer includes oxides. In various implementations,various semiconductor wafers may be used for image sensor dies. The viasprovide a pathway for electrical connection between the sensor siteinterconnection 86 and other areas of the die and associated packaging.Referring to FIG. 8, the image sensor wafer 88 is illustrated afterhaving been thinned. Thinning may be performed through any methoddescribed herein. As illustrated, the thinning exposes the vias 90 forinterconnection. A redistribution layer 92 is illustrated after havingbeen formed on a side of the wafer 88 opposite the sensing region 94. Insome implementations, a passivation layer may be formed on the waferopposite the sensing region. Referring to FIG. 10, the method from FIG.8 includes flipping the image sensor wafer 102. The wafer may be coupledto a backgrinding tape and flipped while being mounted to new tape. Invarious implementations, the wafer may be singulated into individual dieafter thinning. The individual die may be then flipped as part ofsemiconductor package manufacturing using a pick and place process intoa carrier tape.

Referring to FIG. 9, the method implementation for the wafer/dieillustrated in FIG. 7 includes thinning the image sensor wafer 96 on abackside of the wafer, opposite the sensing region of the die. The wafermay be thinned using any method described herein such as by non-limitingexample, backgrinding, wet etching, lapping, any combination thereof, orany method for removing excess material from the back of a wafer. Aredistribution layer has been added to the back of the wafer andinterconnects have been coupled thereto. The interconnects may include,by non-limiting example, solder balls, gold bumps, copper studs, nickel,lead/tin, or any other solder material. In FIG. 11, the wafer/dieimplementation illustrated in FIG. 9 is illustrated after flipping thewafer 104 for further manufacturing processes.

Referring to FIGS. 12-17, various phases after method steps of animplementation of a method of preparing a glass block for use in asemiconductor package are illustrated. Referring to FIG. 12, a glassblock 106 is provided. The glass block may be plain glass or it may behole patterned glass. Referring to FIG. 13, the method includes forminga cavity 108 in the glass block 110. In various implementations, thecavity 108 may be formed by etching. In some implementations, theetching may include dry etching or wet etching. In otherimplementations, the cavity may be formed by casting or otherwiseshaping the glass. In other implementations, the cavity may include twopieces of glass bonded together. In still other implementations, thecavity may include a transparent or translucent material. In variousimplementations, the cavity may have a cuboidal shape.

Referring to FIG. 14, standoffs 112 may be coupled to an inner surface114 of the cavity 116 within the glass. The standoff units may be, bynon-limiting example, polymer, glass, or ceramic in variousimplementations. In some implementations, glass standoffs may beintegrally formed as part of the etching process. In otherimplementations, the standoffs may include polymer materials or otherelectrically insulative materials. When the standoffs are intended forelectrical connection, they may be formed of, by non-limiting example,metal, solder, metal alloys, or a conductive adhesive. Metal for thestandoffs may include gold studs, copper bumps, nickel, lead/tin, orother solder materials. A top view 120 of standoff 124 in a cavity 122of a glass block 126 is illustrated in FIG. 15. In this implementation,four standoffs 124 are illustrated. In other implementations, a standoffmay be a single or two-piece unit distributed around the perimeter ofthe cuboid shape.

Referring to FIG. 16, another implementation of a glass block isillustrated. In this implementation, metal traces 128 are coupled to aninner surface 130 of the cavity 132. A top view of the plurality ofmetal traces 134 coupled to the inner surface of the cavity 136 isillustrated in FIG. 17. The metal traces may be formed of, bynon-limiting example, copper, gold, lead/tin, and other electricallyconductive metals.

Referring to FIGS. 18-25, various package implementations followingvarious steps of an implementation of a method of forming asemiconductor package are illustrated. FIG. 18 illustrates the packageafter forming a cavity 138 in a glass block 140. In variousimplementations, the cavity may be formed using any methodimplementation described herein. The glass used may be a plain glass insome implementations. Referring to FIG. 19, package is illustrated aftercoupling two or more standoffs 142 to an inner surface 144 of the cavity146. The standoff units may be coupled to the glass through an adhesivematerial. In implementations not requiring the one or more standoffs tobe electrically conductive, the standoffs may be of materials includingpolymers, glass, ceramic or other non-electrical material and any othermaterial disclosed herein. In implementations using glass for thestandoff material, the standoffs may be integrally formed as part of theetching process. In other implementations, the standoffs may for formedof electrically conductive materials such as, by non-limiting example,metal, solder, or conductive adhesives. The metals may include goldbumps, copper bumps, lead/tin, nickel, and other suitable metals. Themethod may further include bonding a semiconductor device 148 to the twoor more standoff units 150 as illustrates in FIG. 20.

Referring to FIG. 21, the package is illustrated after sealing thesemiconductor device 152 within the cavity using an opaque fillingmaterial 154. The opaque filling material 154 may seal any gaps betweenthe glass block 153 and the semiconductor device 152. The opaque fillingmaterial 154 may also block light from contacting an edge of thesemiconductor device. The opaque filling material may blockpredetermined wavelengths of light and may allow other wavelengths oflight to get through. The predetermined wavelengths that are blocked mayinclude light in the visible light spectrum in various implementationsor other undesired wavelengths of electromagnetic radiation. The glasscavity structure may protect the sensor and provide stable standoffrequirement of higher gap 156 of sensor to glass.

Referring to FIG. 22, in various implementations, a substrate 158 ispicked through a pick and place system and readied for placement overthe semiconductor device 160. The substrate may be singulated or formedindividually. In various implementations, the substrate may be anembedded substrate. In implementations with an embedded substrate, oneor more devices may be embedded within the substrate. The embeddeddevices may be passive devices, active devices, or a combination of bothpassive and active devices. FIG. 23 illustrates the package aftermechanically and electrically coupling the substrate 158 to thesemiconductor device 160 and over an opening of the cavity in the glassblock 162. Referring to FIG. 23, two solder balls 164 are illustrated inelectrical contact with the first side of the semiconductor device. Theuse of flip chip bonding may provide for a narrow space of the die edgeto the sensor array to be designed. Flip chip packaging may provide theshortest possible connections, lower inductance, higher frequency,better noise control, higher density, small device footprints, and lowerdevice profiles. Flip chip processing can also utilize the full activearea of the first side of the die.

FIG. 24 illustrates the package after underfilling a gap 166 between thesubstrate 168, the semiconductor device 167, and edges of the glassblock 170 surrounding the cavity. As illustrated in FIG. 24, the gap isfilled with a fill or underfill 172 material. The underfill material mayinsulate the electrical connections and provide a seal for thesemiconductor package. FIG. 25 illustrates the package after couplinginterconnects 180 to a first side of the substrate 182 as illustrated inFIG. 25. The interconnects may include a ball grid array (BGA), landgrid array (LGA), pin grid array (PGA), individual solder balls, goldbumps, copper bumps, lead/tin bumps, or other suitable interconnectmaterial used in semiconductor packages.

Referring to FIG. 26-33, a semiconductor package implementation isillustrated after various processing steps of an implementation of amethod of forming a semiconductor package. Referring to FIG. 26, a glassblock 184 following forming a cavity therein is illustrated. The cavitymay be formed through any method disclosed herein. In variousimplementations, the glass may be hole patterned glass. As illustratedin FIG. 27, the package is illustrated after coupling a plurality oftraces 186 to an inner surface 190 of the cavity 188. In variousimplementations, the traces may be made of gold, copper, nickel,lead/tin, or other electrically conductive materials (includingnon-metallic materials). Referring to FIG. 28, the package isillustrated after bonding a semiconductor device 192 into the cavity194. The semiconductor device may be electrically coupled to the metaltraces through solder balls 196. In other implementations, theinterconnects 196 may include gold stud bumps. In this particularimplementation, the device 192 does not include vias. The device mayinclude a redistribution layer or a passivation layer on the first sideof the die.

Referring to FIG. 29, the package implementation is illustrated afterusing an opaque filling material 198 to seal the semiconductor device200 within the cavity 200. The opaque filling material may seal the gapsaround the semiconductor device 200 to form a hermetic seal. The opaquefilling material may be optically opaque and may block particularwavelengths of light from contacting the edge of the semiconductordevice (and/or may block any other wavelength of electromagneticradiation desired as disclosed in this document). Referring to FIG. 30,a substrate 202 is illustrated having solder balls 206 on a second sideof the substrate. Through pick and place, the substrate 208 isillustrated as being readied to be mechanically and electrically coupledto the semiconductor device and the edges of the glass block 210 asillustrated in FIG. 31.

Referring to FIG. 32, a gap between the substrate 216, the semiconductordevice 220, and the glass block 218 surrounding the cavity is filledwith underfill 214 material. Referring to FIG. 33, the package isillustrated after coupling a ball grid array 22 to a first side of thesubstrate 224. In various implementations, other interconnects types maybe used such as, by non-limiting example, solder balls, land gridarrays, studs, or other suitable interconnects for flip chip packaging.

Referring to FIG. 34-41, a package implementation is illustrated aftervarious processing steps of another implementation of a method offorming a semiconductor package. Referring to FIG. 34, the a glass block226 is illustrated after forming a cavity therein. The cavity may beformed through any of the forming techniques disclosed in this documentincluding dry etching and wet etching. In other implementations, thecavity may be formed through casting. In various implementations, theglass may be hole patterned glass. As illustrated in FIG. 36, the methodalso includes coupling a plurality of traces 228 to an inner surface 230of the cavity 232. In various implementations, the traces may includegold, copper, nickel, lead/tin or other electrically conductivematerials (including non-metallic materials). Referring to FIG. 36, thepackage is illustrated after bonding a semiconductor device 234 into thecavity of the glass block 236. The semiconductor device 234 may beelectrically coupled through a flip chip process by the solder ballscoupling with the metal traces. In this particular implementation, thesemiconductor device 234 includes vias 238 extending from the sensorsite interconnections to the redistribution layer 234 on the first sideof the semiconductor device.

Referring to FIG. 37, the package is illustrated after using an opaquefilling material 242 to seal the semiconductor device 246 within thecavity 244. The filling may be optically opaque to block particularwavelengths of light from contacting the edge of the semiconductordevice including any wavelength of electromagnetic radiation disclosedin this document. Referring to FIG. 38, a substrate 248 may be preparedhaving solder balls 250 on a second side of the substrate. FIG. 39illustrates the package after mechanically and electrically coupling thesubstrate 252 to the semiconductor device 256 and the edges of the glassblock 254. The substrate may be handled using a pick and place systemduring this process. In this particular implementation, four solderballs are used in the flip chip method of bonding. Here, the substrateis electrically coupled to the semiconductor die both through a firstside of the die and around the die through the metal traces. This is incontrast to the package formed and illustrated in FIG. 33, where theelectrical connection go around the die rather than through the die.

Referring to FIG. 40, the package is illustrated after underfilling agap between the substrate 260, the semiconductor die, and the sides ofthe glass block 262 using an underfill material 258. The underfillmaterial may act as an insulator for the electrical connections betweenthe substrate and the die. The underfill material may also form ahermetic seal around the die and perform any of the functions disclosedwith respect to fill materials. Referring to FIG. 41, the package isillustrated after coupling a ball grid array 266 or other interconnectsto a first side of the substrate 268. In various implementations, otherinterconnects may be used, including, by non-limiting example, solderballs, land grid arrays, studs, or other suitable interconnects for flipchip packaging.

In places where the description above refers to particularimplementations of semiconductor packages and implementing components,sub-components, methods and sub-methods, it should be readily apparentthat a number of modifications may be made without departing from thespirit thereof and that these implementations, implementing components,sub-components, methods and sub-methods may be applied to othersemiconductor packages.

What is claimed is:
 1. A semiconductor package comprising: asemiconductor device comprised within a cavity within a glass block; asubstrate coupled with a first side of the semiconductor device and twoor more edges of the glass block; one or more traces extending along oneor more of the two or more edges of the glass block; an opaque materialbetween a side surface of the semiconductor device and an inner surfaceof the cavity over the one or more traces; and an air gap between theglass block and the semiconductor device; wherein the opaque material isconfigured to block light from contacting the side surface of thesemiconductor device.
 2. The semiconductor package of claim 1, furthercomprising one or more solder balls physically coupling thesemiconductor device with the one or more traces.
 3. The semiconductorpackage of claim 1, further comprising a fill material comprised betweenthe substrate and the semiconductor device.
 4. The semiconductor packageof claim 1, wherein the semiconductor device is an image sensor.
 5. Thesemiconductor package of claim 2, further comprising two or more solderballs acting as two or more standoff structures between the inner cavitywithin the glass block and a second side of the semiconductor device. 6.The semiconductor package of claim 1, wherein the cavity has a shapethat is cuboidal.
 7. The semiconductor package of claim 1, wherein thesubstrate is physically coupled with the one or more traces through asolder ball.
 8. The semiconductor package of claim 7, wherein the solderball is located outside a perimeter of the semiconductor device andoutside a perimeter of the cavity in the glass block thatcorrespondingly extends around the perimeter of the semiconductordevice.
 9. A semiconductor package comprising: a semiconductor devicecomprised within a cavity within a glass block; a substrate coupled witha first side of the semiconductor device and two or more edges of theglass block; one or more traces extending along one or more of the twoor more edges of the glass block; an opaque material between a sidesurface of the semiconductor device and an inner surface of the cavity;and an air gap between the glass block and the semiconductor device;wherein the opaque material is configured to block light from contactingthe side surface of the semiconductor device.
 10. The semiconductorpackage of claim 9, further comprising one or more solder ballsphysically coupling the semiconductor device with the one or moretraces.
 11. The semiconductor package of claim 9, further comprising afill material comprised between the substrate and the semiconductordevice.
 12. The semiconductor package of claim 9, wherein thesemiconductor device is an image sensor.
 13. The semiconductor packageof claim 12, further comprising two or more solder balls acting as twoor more standoff structures between the inner cavity within the glassblock and a second side of the semiconductor device.
 14. Thesemiconductor package of claim 9, wherein the cavity has a shape that iscuboidal.
 15. The semiconductor package of claim 9, wherein thesubstrate is physically coupled with the one or more traces and with twoor more vias comprised in the semiconductor device through four or moresolder balls.
 16. The semiconductor package of claim 15, wherein two ofthe four or more solder balls are located outside a perimeter of thesemiconductor device and outside a perimeter of the cavity in the glassblock that correspondingly extends around the perimeter of thesemiconductor device.
 17. A method of forming a semiconductor package,the method comprising: forming a cavity within a glass block; forming anair gap between the semiconductor device and glass block throughcoupling a semiconductor device into the cavity; sealing thesemiconductor device within the cavity using an opaque filling material;mechanically and electrically coupling a substrate to the semiconductordevice and over an opening of the cavity; underfilling a gap between thesubstrate, the semiconductor device, and a side of the glass blocksurrounding the cavity with an underfill material; wherein the opaquefilling material is configured to block light from contacting an edge ofthe semiconductor device.
 18. The method of claim 17, further comprisingcoupling a ball grid array to a second side of the substrate.
 19. Themethod of claim 17, further comprising vias comprised within thesemiconductor device.
 20. The package of claim 17, wherein mechanicallyand electrically coupling a substrate to the semiconductor devicefurther comprises using solder balls.